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Data Path Bit Width
Coefficient Modes
Constant Coefficient Mode
In the single set Constant coefficient mode, the coefficients entered at the configuration time are copied onto
the coefficient ROM. This initial copying happens once, on asynchronous reset signal NGRST that is
normally asserted upon powering-on the FPGA device. A mechanism built into the core runs the process
automatically. No action is required.
It is possible to refresh the ROM contents by asserting the clock-wide COEF_REF signal, if required. Then
the core runs the copying sequence again. The core generates the optional pulse CORE_REF_DONE, once
the initial or subsequent copying is completed. The copying takes approximately 8*TAPS clock intervals.
The core keeps the signal DATAO_VALID deasserted until copying is completed.
Multiple Constant Coefficient Sets
In this mode, the filter can switch between k pre-configured coefficient sets. Figure 38 shows the coefficient
ROM in this mode. The core maintains two cache style pages where it is convenient to store the current set
and the set the filter is expected to use next. Then the switch from a current set to the next one takes a few
clock intervals. After the switch, the page that used to store the active set is vacant. It can be used for the
next coefficient set.
CoreFIR automatically configures a coefficient ROM to use dual-page memory in Multiple set or Reloadable
mode. The COEF_SEL 4-bit input controls a MUX that selects one of the constant coefficient sets. On
asserting and deasserting the COEF_REF signal, the core starts copying the selected set on the auxiliary
page of the ROM. In the meantime, the filter engine keeps using current coefficient set stored on the active
page. Once the copying is completed, the core issues the optional signal COEF_REF_DONE but the
coefficients are not propagated to the filtered engine yet. This only takes place when the COEF_ON signal is
issued, which swaps active and auxiliary pages. The swapping takes up to four clock intervals. The input
data samples coming after that time will be properly processed.
After initial power-up, the Active page does not contain any coefficient set. Therefore the core does not
produce a meaningful result until the auxiliary page gets filled with a valid set and becomes the active page
after the COEF_ON signal comes in. The core downloads the coefficient set 0 (COEF_SEL = 0) on power-
on. As a result, the interpolation filter uses the coefficient set 0 upon power-on.
Coefficient ROM
COEF_ON
swap pages
Active Page
MAC Engine
c(i)_set_0
c(i)_set_1
c(i)_set_2
...
COEF_SEL
Auxiliary Page
c(i)_set_k
COEF_REF
COEF_REF_DONE
Figure 38 · Two-Page Coefficient Storage in Multiple Set Mode
CoreFIR v8.5 Handbook
43
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